1. Field of the Invention
The present invention relates to a PLL (Phase Locked Loop) circuit, and a recording or reproducing apparatus such as a hard disk drive (HDD) or the like, in which the PLL circuit is used as a clock recovery circuit for generating a clock, based on reproduce information.
2. Description of the Related Art
A basic configuration of a PLL circuit is shown in FIG. 1. Referring to FIG. 1, a phase comparator 1 compares the phases of an oscillation frequency generated from a voltage-controlled oscillator (VCO) 4 and an input signal frequency and supplies information (UP/DOWN) about the error between the phases to a charge pump circuit 2. The charge pump circuit 2 outputs a current Iout pulse-width modulated based on the phase-error information (UP/DOWN) outputted from the phase comparator 1. The output current Iout is smoothed by a loop filter 3 composed of a capacitor 3c and a resistor 3r. A dc output voltage of the loop filter 3 results in a control voltage for the voltage-controlled oscillator 4 and controls its oscillation frequency.
A transient characteristic of the PLL circuit constructed as described above is represented by a natural angular frequency .omega.n and a damping factor .zeta.. Assuming now that the gain of the charge pump circuit 2 is KI, the gain of the voltage-controlled oscillator 4 is KVCO, the capacitance of the capacitor 3c is C and the resistance of the resistor 3r is R, the natural angular frequency .omega.n and damping factor .zeta. are given by the following equations: ##EQU1##
The natural angular frequency .omega.n indicates a loop band of the PLL circuit and simultaneously indicates an Acquisition speed of the PLL circuit. On the other hand, the damping factor .zeta. indicates the stability of a loop.
When the input signal frequency varies, the PLL circuit needs to change the natural frequency .omega.n. When the natural angular frequency .omega.n is changed according to the use of the PLL circuit, the gain KI of the charge pump circuit 2 and the gain KVCO of the voltage-controlled oscillator 4 are controlled. At this time, the damping factor .zeta. is varied in proportion to the natural angular frequency .omega.n. Therefore, the time constant CR of the loop filter 3 must be changed to maintain the damping factor .zeta. at a predetermined value.
Since the capacitor needs an area in the case of the idea that the PLL circuit is brought into an IC, it is difficult to vary the capacitance C of the capacitor 3c upon changing the time constant CR of the loop filter 3. Thus, a configuration has heretofore been adopted in which as shown in FIG. 2, the time constant CR of a loop filter 3 is changed by connecting a plurality of resistors 3r1, 3r2 and 3r3 and a plurality of switches 5s1, 5s2 and 5s3 to a capacitor 3c and performing switching between their resistance values under switching control.
However, the conventional PLL circuit constructed as described above is still unfit for the implementation therefore in an IC according to its use because when it is necessary to vary the time constant CR of the loop filter 3 in multistage form, the resistor 3r and the switch 3s are arranged in large numbers and they must be suitably switching-controlled.